1. Field of the Invention
This invention relates to the manufacture of integrated circuits and in particular to the manufacture of integrated circuits having transistors with polycrystalline channels.
2. Art Background
Substantial miniaturization has occurred in the production of integrated circuits over the last decade. A variety of approaches are being employed to further effect this miniaturization. One approach involves stacking transistors vertically so that fewer transistors per circuit element are formed in the single crystal substrate and thus higher overall device density is achieved.
In any vertical assemblage of transistors, the underlying transistors, those formed in single crystal silicon, are fabricated by employing the highly defect-free silicon substrate for critical electrical regions such as the channel. Overlying transistors are produced by depositing polycrystalline semiconductor device layers on an insulating region formed on the transistors of the substrate. Since these overlying transistors are produced on an electrically insulating material, in the absence of substantial processing complications they are typically formed in polycrystalline materials. For example, as shown in FIG. 1 for an inverted configuration as used in static random access memory, a polycrystalline region is deposited on silicon oxide separating the overlying from underlying transistors and patterned to form the gate, 12, of the overlying transistors. An inverted configuration involves a transistor with gate region 12 closer to the substrate than channel region 9. A gate oxide region 53 is formed and suitably patterned. A second polycrystalline layer, 9, is deposited to form the channel and appropriately patterned. This layer should be thin to avoid excessive off-state current. Appropriate regions of this layer are heavily doped by ion implantation to form source and drain regions 10 and 11. A third oxide region, 5, is formed to electrically isolate subsequent electrical contacts from the channel and patterned to allow contact to source and drain regions 10 and 11. A third polycrystalline region, 4, is then deposited, doped and patterned to form these source and drain contacts. This additional layer is required to avoid excessive resistance in runners and contacts to the unaugmented channel layer.
This fabrication sequence involves the expense and complications of a large number of steps. This shortcoming is thought necessary to insure a thin channel region 9 and a relatively thick source contact, drain contact and interconnect regions. As mentioned above, the channel region should be thin so that excessive off-state current is not obtained, while the source contact, drain contact and interconnect region 4 is thick to avoid excessive resistance in the source and drain contacts and interconnects. Thus limitations on geometry and electrical properties have strongly influenced the fabrication procedure. (It should be noted that this exemplary description is in terms of an inverted transistor. However, an equivalent description and formation is possible where the gate is instead formed overlying the channel region 9, i.e., an upright configuration.)
Since the overlying transistors are fabricated in polycrystalline material, they are of significantly poorer quality than their underlying counterparts. However, there are many circuits where some parameters of the transistor, i.e., the on-current, for a substantial portion of the active devices is not demanding. For example, in inverter circuits, generally the p-channel device has substantially relaxed electrical requirements compared to their n-channel counterparts used in Complementary Metal Oxide Semiconductor (CMOS) configurations. Typically, in demanding circuits the n-channel current in the on-state relative to the off-state should be 10.sup.10 to 10.sup.12 times larger. In comparison, for an inverter the current in the on-state for the p-channel device need only be 10.sup.3 to 10.sup.5 times higher.
Nevertheless, as discussed, to maintain even these relaxed electrical properties in a vertical configuration, material processing complexity arises. The complications attendant this vertical processing reduce its attractiveness as compared to the conventional method of increasing device density by decreasing device size without vertical stacking. If processing complications could be reduced in a vertical configuration, such geometry would become substantially more attractive.